Multichip wafer level system packages and methods of forming same

ABSTRACT

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of application Ser. No.10/229/914, filed Aug. 27, 2002, pending.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to semiconductorpackaging. More particularly, the present invention relates to waferlevel multichip packaging such as, for example, a system in a packagesolution.

[0004] 2. State of the Art

[0005] Semiconductor chips (also referred to as die/dice herein) arefound in many electronic products today. As semiconductor dice getsmaller and more complex, the problem of making electrical connectionsbetween semiconductor dice, connections to carrier substrates such asprinted circuit boards, and connections to intermediate substrates suchas multichip modules which are, in turn, connected to carrier substrateshas been addressed with a variety of constantly evolving solutions.

[0006] One of the earlier solutions included wire bonding from signalconnection devices, such as bond pads of a semiconductor die, to pins orleads of a lead frame contained in a ceramic or plastic package.Finished packages are mounted to a carrier substrate, such as a printedcircuit board, where the pins or leads make electrical connection withcontact pads on the carrier substrate.

[0007] The term “signal connection devices” as used herein regardingsemiconductor devices includes not only contact pads of a substrate andbond pads of a semiconductor device but also I/O connections for asemiconductor device created by adding circuitry from bond pads locatedon the active surface of the semiconductor device to different locationson the active surface of the semiconductor device. Such additionalcircuitry is typically effected using a so-called “redistribution layer”extending over the active surface or a surface of a semiconductor die.

[0008] An evolution of electrical connection technology occurred whenmultiple semiconductor dice were mounted on an intermediate substrate.In this instance, the semiconductor dice are typically connected to alead frame by way of bonding wires. Signals, or electrical connections,required for coupling with an external device, such as a circuit board,are brought out to contact pads, pins or leads of the multichip modulepackage. Other signals or electrical interconnections may be establishedbetween multiple semiconductor dice by way of circuitry formed on theintermediate substrate.

[0009] In these solutions, using wires for connecting a semiconductordie to a substrate and wire bonding processes can create problems. Suchproblems may include, for example, size and pitch (spacing) requirementsfor the bond pads of the semiconductor die and contact pads of thesubstrate; inductance in the signals due to the long curved wires; wirebond breakage and wire sweep causing shorting between adjacent wires;and high signal frequency semiconductor dice making the wire bondingprocess difficult and expensive.

[0010] Flip-chip technologies using solder balls or bumps have helped toalleviate some of these problems. For example, instead of wire bonding,conductive bumps such as, for example, balls of solder may be formed atthe locations of the bond pads of a semiconductor die. A specializedlead frame, a dielectric tape carrying circuit traces as used in tapeautomated bonding processes, or other carrier substrates such as aprinted circuit board may have electrical connection locations such asterminals which correspond to the placement of the solder balls on thebond pads of the semiconductor die. The semiconductor die is “flipped”upside down so the solder balls are placed, for example, on the contactpads of a carrier substrate. A solder reflow. process heats the solderballs until the solder begins to flow and bond with a correspondingcontact pad of a carrier substrate. Upon cooling, the solder forms bothmechanical and electrical connections between the carrier substrate andthe semiconductor die. This packaging solution may alleviate at leastsome of the inductance problems, allowing for higher frequencyperformance and better signal integrity of the semiconductor die. Also,to a certain extent, it allows the contact pads of a substrate whereconductive bumps were formed to be larger, more widely pitched andplaced anywhere on the semiconductor die active surface rather than justaround the periphery or down the center thereof.

[0011] Chip scale packaging has evolved from various standard flip-chipprocesses to a configuration wherein the size of a package is reduced toonly slightly larger than the size of the semiconductor die. Chip scalepackages are typically created using an interposer substrate. Thesemiconductor die, with solder balls or bumps such as described above,is attached and electrically connected to the interposer substrate andan encapsulation material is applied over the chip for protectionthereof from the elements. The interposer substrate can redistributesignal connections to new locations so they are physically positioned ina desired pattern or arrangement, or to just a different pitch moresuitable for mounting to an interposer substrate. An additional set ofconductive bumps may then be formed at other contact pad locations onthe interposer substrate. The resulting package may then be attached toa carrier substrate such as a printed circuit board.

[0012] Chip scale packaging enables small packages using desired ballgrid arrays or fine ball grid arrays. However, the interposer substrateis typically made of an organic material which is the same as, orsimilar to, that used for printed circuit boards. There isconventionally a significant mismatch in the coefficients of thermalexpansion (CTE) of the interposer substrate and the semiconductor die,often resulting in substantial stress on the mechanical and electricalinterconnections formed between the semiconductor die and interposersubstrate (e.g., a reflowed solder connection) during the normal thermalcycling during normal operation of the semiconductor die. The use of aceramic substrate may alleviate some of the CTE mismatch concerns but ata considerably higher cost relative to more conventional interposersubstrates.

[0013] Another advance in the area of multichip modules includes waferscale integration. Wafer scale integration generally comprisesfabricating multiple types of functional semiconductor dice on a singlewafer. For example, a four-chip system may be created by placing amicroprocessor next to a memory controller and two memory-typesemiconductor dice. This pattern may then be repeated across the entirewafer. After fabrication, the wafer is sawed into individual segmentswith each segment containing the four different functions. However, thisapproach has not been a very satisfactory solution due to yield problemscreated by the variations in processes for forming processors andvarious types of memory-type semiconductor dice. For example, if adefect causes any one of the four functions to be inoperable, the entiresegment is defective and not usable.

[0014] In addition to that described above, there have been advances inbump technologies where the conductive bumps act as the signalconnection device. Conventional solder bumps, in some cases, have beenreplaced by stud bumps. Stud bumps have conventionally been gold, butcopper and plated-type stud bumps have also been used recently. The studbumps may actually comprise short wires or wire stubs applied to asemiconductor die using a conventional wire bonding process. Studbumping has the advantages of using a more cost effective wire bondingprocess for application of the bumps in comparison to the more complex,multistep solder bumping process. Further, conductive andconductor-filled adhesives have also been employed to attach theconductive bumps to a carrier substrate. The conductive orconductor-filled adhesive may provide an amount of flexibility to themechanical and electrical connection, thereby compensating for some ofthe problems associated with the mismatch of CTE often associated withsolder bump processes as discussed above.

[0015] However, in light of the advances made in fabricatingsemiconductor device packages, there is a continued need for a reliable,cost effective solution with a higher integration of various functionalsemiconductor dice in a single package to produce, for example, a systemon a semiconductor die solution. There is also a need to create smallerpackages with more consistent thermal expansion properties whileenabling the redistribution of signal connection devices of the varioussemiconductor dice to a more convenient, possibly denser, and optionallystandard configuration for attachment to a carrier substrate.

[0016] Finally, it would be advantageous to provide a system on a chippackaging solution using known good dice, such use thereby increasingthe yield of usable packages and, thus, improving the efficiency andcost effectiveness associated with producing such packages.

BRIEF SUMMARY OF THE INVENTION

[0017] The present invention includes new packaging implementationmethods to solve or at least reduce some of the problems encountered inthe prior art. Generally, the present invention provides a multichipmultilayer system on a chip-type solution. Greater integration isaccomplished using a plurality and variety of known good dice containedwithin cavities formed in a separate silicon substrate. The term“variety” includes semiconductor dice of not only different types(microprocessor, logic, memory, etc.) but functionally similarsemiconductor dice of different dimensions and I/O arrangements. hepresent invention also contemplates the use of so-called “known gooddie,” or KGD, as the semiconductor dice to be packaged.

[0018] The present invention enables the use of processes for makingsilicon-type semiconductor dice for creating additional redistributionand interconnect layers in the same plane or same planes verticallyoffset from the multichip arrangement. These additional layers may thenbe terminated with conductive bumps, optionally in a standardconfiguration, at the top layer for typical flip-chip application of theassembly to a carrier substrate such as printed circuit board or othermultichip module substrate.

[0019] According to one embodiment of the present invention, a pluralityof cavities is etched into the top of a substrate, such as a siliconwafer. The cavities are sized, configured and located to physicallyreceive signal connection devices of a plurality and variety of types ofsemiconductor dice. The signal connection devices on the semiconductordie may be formed, for example, as gold stud bumps. A semiconductor dieattach material adhesive with a high dielectric constant is applied tothe top surface of the substrate and in the cavities. The substrate, awafer, having the semiconductor dice thereon is flipped upside down andplaced such that the signal connection devices are received by thecavities with the bond pads on the active surface of each semiconductordie making contact with the die attach material. A layer of moldingcompound is formed over the top of the substrate and over the backs ofthe various semiconductor dice. This molding compound creates thepackage structure, adds mechanical stability, and protects thesemiconductor dice from the elements. A portion of the back surface ofthe substrate is removed, such as by back-grinding or another suitableprocess, until the signal connection devices are exposed through theback surface of the substrate. With the signal connection devicesexposed, a dielectric layer is formed over the entire back surface ofthe wafer. The dielectric layer is then etched to expose the signalconnection devices for use in connection to higher-level packaging.

[0020] According to another embodiment of the invention, a plurality ofcavities is formed in the top surface of a substrate. The cavities areformed to receive the substantial entirety of each of the varioussemiconductor dice of a plurality to be packaged. Therefore, thecavities are individually sized and configured to correspond with thebond pads of each individual semiconductor die type that is used. It maybe desirable to configure the cavities such that the active surface of asemiconductor die placed therein is approximately flush with the surfaceof the substrate. A die attach material is placed in the die cavitiesand the semiconductor dice are placed in the cavities with the activesurface of each semiconductor die facing upwards and such that the backsurfaces of the semiconductor dice contact the die attach material inthe bottoms of the cavities. A dielectric layer is formed over the topsof the semiconductor dice, over the top of the substrate and into anygaps between the dice and the cavity sidewalls. Finally, vias are formedin the dielectric layer to expose signal connection devices on thevarious semiconductor dice.

[0021] The semiconductor device packages according to the presentinvention may further undergo a redistribution layer (RDL) process toform signal interconnections between semiconductor dice of the packageor to redistribute signals from the signal connection device locationsof the various types of semiconductor dice to more convenient andoptionally standard locations for interconnection with an externaldevice or component. In the redistribution layer process, a metal layeris deposited and patterned to create an interconnect layer from theexposed signal connection device (e.g., contact pad or conductive bump)locations to other locations.

[0022] Additional signal layers may be formed if so desired. This signallayering process includes three primary acts: first, a new dielectriclayer is formed on the wafer; next, vias are formed in the dielectriclayer so connections to an underlying metal layer may be formed; andfinally, a new layer of metal is deposited and patterned to create aninterconnect on this new layer as well as connections to the underlyinglayer through the vias.

[0023] Once the signal layering process is completed for the number ofadditional interconnect layers desired, a final interconnect layer isformed. At this juncture, a new dielectric layer is formed on the wafer.Next, openings are formed in the dielectric layer sufficient for theformation of new signal connection devices and for connections to theunderlying metal layer. Finally the new signal connection devices, suchas conductive bumps in the form of solder balls, are formed in theopenings.

[0024] At this point, if desired, testing may be accomplished throughthe solder balls on each of the individual silicon wafer segmentscontaining a complete system on a wafer segment including various typesof semiconductor dice. Finally, the process is completed by sawing thewafer into multichip segments, creating a plurality of individualmultichip multilayer systems on chip packages, each ready for test andassembly.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0025] In the drawings, which illustrate what is currently considered tobe the best mode for carrying out the invention:

[0026]FIGS. 1A through 1F show cross-sectional views of a system packageat various stages of fabrication according to an embodiment of thepresent invention;

[0027]FIGS. 2A through 2D show cross-sectional views of a system packageat various stages of fabrication according to another embodiment of thepresent invention;

[0028]FIGS. 3A through 3F show cross-sectional views of a system packageincluding a redistribution layer according to another embodiment of thepresent invention;

[0029]FIG. 4 is a plan view showing a wafer including a plurality ofsections, each containing a plurality of semiconductor dice, accordingto the present invention;

[0030]FIG. 5 is a plan view showing a plurality of multichip modulesaccording to the present invention on a memory device; and

[0031]FIG. 6 is a block diagram showing a memory device including atleast one of the multichip modules according to the present inventionincorporated in a computing system.

DETAILED DESCRIPTION OF THE INVENTION

[0032] Referring to drawing FIGS. 1A through 1F, the process ofmanufacturing a packaged semiconductor device according to an embodimentof the present invention is shown. Illustrated in drawing FIG. 1A is across-sectional view of a bare substrate 102. The substrate 102 materialmay include a conventional silicon wafer or other bulk silicon substratesuch as is well known in the art. However, it is understood that thissubstrate 102 may comprise other well-known substrates such as a ceramicor other suitable material. A plurality of cavities 105 is formed in thetop surface 104 of the substrate 102, such as through a conventionalanisotropic silicon etching process. The cavities 105 are each definedby a cavity base 108 and cavity walls 110. As indicated in drawing FIG.1A, the cavity walls 110 may be formed to exhibit a generallyrectangular geometry in cross section such that the cavities 105 aregenerally cubic in shape. However, the cavities 105 may exhibit othergeometries such as, for example, cylindrical, conical, frustoconical,pyramidal, frustopyramidal or semispherical.

[0033] Referring next to drawing FIG. 1B, the top surface 104 of thesubstrate 102 is coated with a layer of die attach material 112 such asa die attach material which may be applied in a generally liquid formand then soft-baked or cured to a B-stage. The die attach material mayinclude epoxy resins and polyimides, as well as organic andpolymer-based resins. Exemplary die attach materials include resinsderived from B-stage benzocyclobutene (BCB) and which are available fromDow Chemical Company of Midland, Michigan. The die attach material 112may be applied to the substrate using a conventional spin or spraycoating process wherein the top surface 104 of the substrate 102 iscoated and the cavities 105 are filled with the die attach material 112as will be appreciated by those of ordinary skill in the art. The dieattach material 112 material may desirably exhibit, for example, adielectric constant up to approximately three to ensure adequateelectrically insulative properties. It is noted that the soft-bake orB-stage curing of the die attach material helps to prevent movement ofthe semiconductor dice 114 relative to the substrate 102 duringsubsequent baking or curing operations.

[0034] A plurality of discrete semiconductor dice 114is provided, eachhaving a plurality of signal connection devices, shown as conductivebumps 116, attached to bond pads 115. The semiconductor dice 114 areplaced upside down with the conductive bumps 116 positioned in thecavities 105 and with the active surface 118 of the semiconductor dice114 in contact with the die attach material 112. It is noted that thesize of the cavities 105 may be etched slightly larger in breadth and/ordepth than the size of the conductive bumps 116 in order to ensureproper fit of the conductive bumps 116 within the cavities 105. Theconductive bumps 116 may be formed, for example, as gold stud bumpsapplied with a conventional wire bond process. Other signal connectiondevices, such as copper stud bumps or plated-type stud bumps may also beused. Although drawing FIGS. 1C through 1F show the conductive bumps 116as generally spherical balls, the conductive bumps 116 may actually beformed in other shapes, including pillars and columns.

[0035] In addition, for simplicity, drawing FIGS. 1A through 1F show asingle row of conductive bumps 116 positioned extending down thelongitudinal axis of each of the semiconductor dice 114, whichlongitudinal axis is oriented transverse to the plane of the page.However, other conductive bump arrangements such as, for example, anarrangement around the periphery of a semiconductor die 114 or an arrayof conductive bumps 116 across the active surface 118 of a semiconductordie 114 are also within the scope of the present invention. Furthermore,the semiconductor dice 114 may be of more than one functional varietyappropriately arranged so as to create what is referred to as a systemon a chip, as will be described in further detail below.

[0036] With the semiconductor dice 114 attached to the substrate 102, amolding or encapsulating layer 119 is formed over the top surface 104 ofthe substrate 102 and the back side 120 of the semiconductor dice 114 asshown in drawing FIG. 1D. The molding layer 119 may be any of a varietyof compounds known in the art for the purpose of encapsulating thesemiconductor dice 114 and substrate 102 to form a typical chip scalepackage. The molding layer 119 may include a filled polymer and maydesirably comprise a material having properties sufficient to allow itto withstand temperatures of up to about 300° C. without substantialdegradation thereof.

[0037] After the molding layer 119 is disposed on the top surface 104 ofthe substrate 102 and properly cured, a portion of the substrate 102along its bottom surface 106 is removed as is shown in drawing FIG. 1E.It is noted that, for purposes of clarity, the assembly, as shown indrawing FIG. 1E (as well as in subsequent drawing FIG. 1F), is flippedupside down relative to that which is shown in drawing FIGS. 1A through1D. The portion of material may be removed from the bottom surface 106of the substrate 102 by techniques such as back-grinding, abrasiveplanarization techniques such as chemical-mechanical planarization(CMP), etching or an atmospheric downstream plasma (ADP) process offeredby Tru-Si Technologies of Sunnyvale, Calif. which is known by those ofordinary skill in the art. Material is removed from the bottom surface106 of the substrate 102 until the conductive bumps 116 are exposed,creating a new bottom surface 106′ of the substrate 102, as shown inFIG. 1E. With the conductive bumps 116 exposed, a system on a chipstructure has been created with an array of exposed conductive bumps116.

[0038] To prepare the wafer for a redistribution layer (RDL) process, adielectric layer 122 is formed covering the new bottom surface 106′ ofthe wafer and the conductive bumps 116, as shown in drawing FIG. 1F.Finally, a plurality of vias or openings 124 is formed in the dielectriclayer 122 over the conductive bumps 116, such as with a conventionaletching process. The assembly may then be subjected to an RDL process toredistribute or relocate the signals to an arrangement of signal deviceor input/output connections.

[0039] Before describing the redistribution layer process, anotherembodiment of the present invention is described as shown in drawingFIGS. 2A through 2D. The process begins, as in the previously describedembodiment, with a substrate 202 such as a silicon wafer as shown indrawing FIG. 2A. Again, cavities 205 are formed in the substrate 202,each cavity being defined by a cavity base 208 and cavity walls 210.However, in the presently described embodiment, the cavities 205 are ofa size sufficient to receive substantially the entirety of eachindividual semiconductor die 214. Additionally, the cavities 205 areformed to a depth short of back side 206 sufficient to allow the activesurface 220 of the semiconductor dice 214 to be substantially flush withthe top surface 204 of the substrate 202. It is noted that, sincedifferent types of semiconductor dice 214 may be used, the cavities 205may accordingly differ in size and shape from one cavity to another.

[0040] As shown in drawing FIG. 2B, a layer of die attach material 218is applied in the cavities 205. Discrete semiconductor dice 214 are thenplaced in the cavities 205 with the active surface 220 of thesemiconductor dice 214 facing upwards and the back surface 216 of thesemiconductor dice 214 being attached to the base 208 of its respectivecavity 205 via the die attach material 218. As shown in drawing FIG. 2C,a first dielectric layer 222 is applied over the top surface 204 of thesubstrate 202 and which may fill in any gaps 221 between the sides ofthe semiconductor dice 214 and the cavity walls 210. The firstdielectric layer 222 may be applied in a conventional process such asspin coating or spray coating. Finally, as shown in drawing FIG. 2D, aplurality of vias or openings 224 is formed in the first dielectriclayer 222, such as by an etching process, thereby exposing the pluralityof underlying signal connection devices shown as bond pads 215.

[0041] The RDL process, which is applicable to both of the exemplaryembodiments discussed above, is shown and described with respect todrawing FIGS. 3A through 3F. Illustrated in drawing FIG. 3A is a generalsubstrate 302 with embedded semiconductor dice 304 and signal connectionopenings 306 representing any embodiment within the scope of theinvention. The process begins, as shown in drawing FIG. 3B, by ametallization layer and patterning process to create a first circuitconnection layer 308 of metal covering the plurality of signalconnection openings 306. In the exemplary embodiments, the signalconnection openings 306 expose either the conductive bumps 116 in theembodiment shown and described with respect to drawing FIGS. 1A through1F or the bond pads 215 in the embodiment shown and described withrespect to drawing FIGS. 2A through 2D. This results in an electricalconnection to the underlying semiconductor dice 304 and creates firstcircuit connection layer 308, shown as circuit lines, to redistributeand possibly connect the signals to other metallization layers.

[0042] The RDL process may incorporate metallization layer depositionand etching processes well known in the art to form the pattern ofopenings and first circuit connection layers 308. Further, the metallayer may be formed of a material including, for example, aluminum,copper, or other alloys known and utilized in the art. It is also notedthat signal connection devices (e.g., the conductive bumps 116 ofdrawing FIG. 1C or the bond pads 215 of drawing FIG. 2C) may be treatedor have an under-bump metallization-type material placed thereon priorto connection with the first circuit connection layer 308 to enhancemetallic adhesion therebetween.

[0043] A predetermined number of additional metal layers may be added ina basic three-step signal connection layering process as shown indrawing FIGS. 3C and 3D. For example, a new additional dielectric layer310 is formed over the previous metal and dielectric layers, coating theentire wafer. Next, a plurality of vias or openings 312 is created inthe dielectric layer 310, such as by etching, exposing the underlyingfirst circuit connection layer 308 at a desired plurality of circuitconnection areas. Finally, a new metallization and patterning processcreates a new circuit connection layer 314, shown in drawing FIG. 3D,making desired electrical connections to the underlying first circuitconnection layer 308 and redistributing signals to new locations,possibly for connection to higher metal layers. For simplicity, thedrawing FIGS. 3A-3D show the formation of only one additional metallayer, However, this process may be repeated a predetermined number oftimes (for example, three times to create three intermediate signalrouting layers), thereby forming a laminate-type structure. Multiplelayers may be desired to create power planes, ground planes, anddifficult signal interconnections not easily accomplished on two signallayers.

[0044] As shown in drawing FIGS. 3E and 3F, a final dielectric layer 316is applied over the previous dielectric layer 310 and circuit connectionlayer 314. Again, a conventional etching process is used to create aplurality of vias or openings 318 in the final dielectric layer 316exposing the underlying circuit connection layer 314. Finally, newsignal device connections 320, such as solder balls or other conductivebumps, are formed in the plurality of openings 318 contacting theunderlying circuit connection layer 314.

[0045] With the new signal device connections 320 formed, if desired,testing could be accomplished through connection with the new signaldevice connections of each of the individual multichip packages.

[0046] Referring now to drawing FIG. 4, an assembly 400 containing aplurality of semiconductor dice 404A-404D (collectively referred to assemiconductor dice 404) is shown according to an embodiment of thepresent invention. The substrate 402 is sawed into individual segments406 along sawing lines 408 to form individual systems on chip moduleswith each segment 406 containing a plurality of semiconductor dice404A-404D possibly of multiple functional varieties. For example,semiconductor die 404A might be a processor, semiconductor die 404Bmight be a memory controller and semiconductor dice 404C and 404D mightbe memory chips. Although FIG. 4 shows a segment 406 containing foursemiconductor dice 404A-404D, it should be understood that the number ofsemiconductor dice within a segment 406 may be some other numberdepending on the design and intended use of the resulting semiconductorpackage.

[0047] Referring now to drawing FIG. 5, a memory device 500, alsoreferred to as a memory module, is shown which incorporates at least onepackaged multichip semiconductor device 510 according to the presentinvention. The memory device 500 includes a carrier substrate 520, suchas a printed circuit board, to which one or more packaged multichipsemiconductor devices 510 may be electrically and operably coupledtherewith. A plurality of electrical connectors 530 is formed on thecarrier substrate 520 to provide input and output connections with anexternal device, such as, for example, the motherboard of a computer, tothe one or more packaged multichip semiconductor devices 510.

[0048] Referring now to drawing FIG. 6, a computing system 600 is shownwhich includes a carrier substrate 602 such as, for example, amotherboard. The carrier substrate 602 may be operably coupled to atleast one processor 604, such as, for example, a central processing unit(CPU), and at least one memory device 606. The memory device 606 mayinclude one or more packaged multichip semiconductor devices 608 such asdescribed above. The carrier substrate 602 is operably coupled with atleast one input device 610 such as, for example, a keyboard, a mouse, asensor or another computing device. The carrier substrate 602 is alsooperably coupled with at least one output device 612 such as, forexample, a printer, a monitor, an actuator or another computing device.Alternatively, the packaged multichip semiconductor device 608 may becoupled directly with the carrier substrate 602.

[0049] Specific embodiments have been shown by way of example in thedrawings and have been described in detail herein; however, theinvention may be susceptible to various modifications and alternativeforms. It should be understood that the invention is not intended to belimited to the particular forms disclosed. Rather, the inventionincludes all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

What is claimed is:
 1. A method of manufacturing a multichip packagecomprising: providing a substrate having a top surface and a bottomsurface; forming a plurality of cavities in the top surface of thesubstrate, each cavity being defined by a base and at least one cavitywall; providing a plurality of semiconductor dice, each semiconductordie having a back surface and a plurality of signal connection deviceson an active surface thereof; applying a layer of die attach material tothe base of each of the plurality of cavities; placing the plurality ofsemiconductor dice in the plurality of cavities with the back surfacesthereof facing the base of the plurality of cavities; forming a firstdielectric layer upon the top surface of the substrate and the activesurfaces of the semiconductor dice including the plurality of signalconnection devices; and forming a plurality of openings in the firstdielectric layer exposing the plurality of signal connection devices. 2.The method of claim 1, further comprising: forming a first circuitconnection layer on the first dielectric layer; and electricallycoupling the first circuit connection layer with the plurality of signalconnection devices through the plurality of openings; forming at leastone additional dielectric layer over the first dielectric layer and thefirst circuit connection layer; forming a plurality of openings in theat least one additional dielectric layer exposing a plurality ofconnection areas on the first circuit connection layer; and forming aplurality of conductive bumps in the plurality of openings of the atleast one additional dielectric layer and electrically coupling theplurality of conductive bumps with the plurality of connection areas onthe first circuit connection layer.
 3. The method of claim 2, whereinproviding a substrate includes providing a substrate comprising asilicon wafer.
 4. The method of claim 3, further comprising forming theplurality of signal connection devices to include bond pads.
 5. Themethod of claim 4, further comprising forming each of the plurality ofcavities to exhibit a depth which is substantially equal to or greaterthan a height of each of the plurality of semiconductor dice.
 6. Themethod of claim 5, wherein applying a layer of die attach materialfurther includes applying a layer of epoxy material.
 7. The method ofclaim 5, wherein applying a layer of die attach material furtherincludes applying a layer of benzocyclobutene.
 8. The method of claim 5,wherein applying a layer of die attach material further comprisesapplying a layer of material exhibiting a dielectric constant of up toabout three.